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1 copyright ? cirrus logic, inc. 2002 (all rights reserved) http://www.cirrus.com preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. cs5351 108 db, 192 khz, multi-bit audio a/d converter features advanced multi-bit delta-sigma architecture 24-bit conversion 108 db dynamic range -98 db thd+n system sampling rates up to 192 khz single-ended analog inputs less than 150 mw power consumption high pass filter or dc offset calibration supports logic levels between 5 and 2.5v linear phase digital anti-alias filtering overflow detection functionally compatible with the cs5361 general description the cs5351 is a complete analog-to-digital converter for digital audio systems. it performs sampling, analog-to- digital conversion and anti-alias filtering, generating 24- bit values for both left and right inputs in serial form at sample rates up to 192 khz per channel. the cs5351 uses a 5th-order, multi-bit delta-sigma modulator followed by digital filtering and decimation, which removes the need for an external anti-alias filter. the cs5351 is ideal for audio systems requiring wide dy- namic range, negligible distortion and low noise, such as a/v receivers, dvd-r, cd-r, digital mixing consoles, and effects processors. ordering information CS5351-KS -10 to 70 c 24-pin soic cs5351-bs -40 to 85 c 24-pin soic cs5351-kz -10 to 70 c 24-pin tssop cs5351-bz -40 to 85 c 24-pin tssop cdb5351 evaluation board voltage reference serial audio interface digital filter high pass filter high pass filter decimation digital filter decimation dac - + s/h dac - + s/h ainr sclk sdout mclk rst vq lrck ainl filt+ m/s hpf mode0 mode1 refgnd v l lp filter lp filter i2s/lj mdiv ? ? sept ?02 ds565pp2
cs5351 2 ds565pp2 table of contents 1 pin descriptions ............................................................................................................... .. 4 2 typical connection diagram ......................................................................................... 5 3 applications .................................................................................................................. ....... 6 3.1 operational mode/sample rate range select .................................................................. 6 3.2 system clocking .............................................................................................................. .. 6 3.2.1 master mode ......................................................................................................... 7 3.2.2 slave mode ........................................................................................................... 8 3.3 power-up sequence .......................................................................................................... 8 3.4 analog connections ........................................................................................................... 8 3.5 high pass filter and dc offset calibration ....................................................................... 9 3.6 overflow detection ........................................................................................................... .. 9 3.6.1 ovfl output timing ........................................................................................... 10 3.7 grounding and power supply decoupling ....................................................................... 10 3.8 synchronization of multiple devices ................................................................................ 10 4 characteristics and specifications ....................................................................... 11 analog characteristics (CS5351-KS/kz) .................................................................. 11 analog characteristics (cs5351-bs/bz) .................................................................. 12 digital decimation filter characteristics .......................................................... 13 dc electrical characteristics................................................................................. 16 digital characteristics ............................................................................................... 16 thermal characteristics............................................................................................ 16 absolute maximum ratings ......................................................................................... 17 switching characteristics - serial audio port ................................................. 18 5 parameter definitions ................................................................................................... 21 6 package dimensions ..................................................................................................... 22 7 addendum ...................................................................................................................... ...... 24 list of figures figure 1. typical connection diagram ............................................................................................ 5 figure 2. cs5351 master mode clocking ....................................................................................... 7 figure 3. cs5351 recommended analog input buffer ................................................................... 9 contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find one nearest you go to important notice "preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "advan ce" product infor- mation describes products that are in development and subject to development changes. cirrus logic, inc. and its subsidiaries ("cirrus") believe th at the infor- mation contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided "as is" witho ut warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information to verify, before placing orders, that in formation being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, inclu ding those pertaining to warranty, patent infringement, and limitation of liability. no responsibility is assumed by cirrus for the use of this information, in cluding use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the prop erty of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the info rmation only for use within your organization with respect to cirrus integrated circuits or other parts of cirrus. this consent does not extend to other copying suc h as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. an export permit needs to be obtained from the competent authorities of the japanese government if any of the products or technologies described in thi sma- terial and controlled under the "foreign exchange and foreign trade law" is to be exported or taken out of japan. an export license and/or quota needs to be obtained from the competent authorities of the chinese government if any of the products or technologies described in this material is subject to the p rc foreign trade law and is to be exported or taken out of the prc. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("critical applications"). cirrus products are not designed, authorized, or warrant- ed to be suitable for use in life-support devices or systems or other critical applications. inclusion of cirrus products in such applications is understood to be fully at the customer's risk. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be tr ade- marks or service marks of their respective owners.
cs5351 ds565pp2 3 figure 4. single speed mode stopband rejection ....................................................................... 14 figure 5. single speed mode transition band ............................................................................. 14 figure 6. single speed mode transition band (detail)................................................................. 14 figure 7. single speed mode passband ripple ........................................................................... 14 figure 8. double speed mode stopband rejection...................................................................... 14 figure 9. double speed mode transition band ............................................................................ 14 figure 10. double speed mode transition band (detail) ............................................................. 15 figure 11. double speed mode passband ripple ........................................................................ 15 figure 12. quad speed mode stopband rejection ...................................................................... 15 figure 13. quad speed mode transition band............................................................................. 15 figure 14. quad speed mode transition band (detail) ................................................................ 15 figure 15. quad speed mode passband ripple........................................................................... 15 figure 16. master mode, left justified sai ................................................................................... 19 figure 17. slave mode, left justified sai ..................................................................................... 19 figure 18. master mode, i 2 s sai .................................................................................................. 19 figure 19. slave mode, i 2 s sai .................................................................................................... 19 figure 20. ovfl output timing .................................................................................................... 19 figure 21. left-justified serial audio interface ............................................................................. 20 figure 22. i 2 s serial audio interface............................................................................................. 20 figure 23. ovfl output timing, i2s format ................................................................................ 20 figure 24. ovfl output timing, left-justified format ................................................................. 20 figure 25. cs5351/cs5361 analog input buffer .......................................................................... 24 list of tables table 1. cs5351 mode control ....................................................................................................... ...... 6 table 2. cs5351 common master clock frequencies ........................................................................ 7 table 3. cs5351 slave mode clock ratios .......................................................................................... 8
cs5351 4 ds565pp2 1 pin descriptions rst 124 filt+ m/s 223 refgnd lrck 322 vq3 sclk 421 ainr mclk 520 vq2 vd 619 va gnd 718 gnd vl 817 vq1 sdout 916 ainl mdiv 10 15 ovfl hpf 11 14 m1 i 2 s/lj 12 13 m0 pin name # pin description rst 1 reset ( input ) - the device enters a low power mode when low. m/s 2 master/slave mode (input) - selects operation as either clock master or slave. lrck 3 left right clock ( input / output ) - determines which channel, left or right, is currently active on the serial audio data line. sclk 4 serial clock ( input / output ) - serial clock for the serial audio interface. mclk 5 master clock ( input ) - clock source for the delta-sigma modulator and digital filters. vd 6 digital power ( input ) - positive power supply for the digital section. gnd 7,18 ground ( input ) - ground reference. must be connected to analog ground. vl 8 logic power ( input ) - positive power for the digital input/output. sdout 9 serial audio data output ( output ) - output for two?s complement serial audio data. mdiv 10 mclk divider (input )- enables a master clock divide by two function. hpf 11 high pass filter enable (input )- enables the digital high-pass filter. i 2 s/lj 12 serial audio interface format select ( input ) -selects either the left-justified or i 2 s format for the sai. m0 m1 13, 14 mode selection ( input ) - determines the operational mode of the device. ovfl 15 overflow (output, open drain) - detects an overflow condition on both left and right channels. ainr ainl 16, 21 analog input ( input ) - the full scale analog input level is specified in the analog characteristics specifi- cation table. vq1 vq2 vq3 17, 20, 22 quiescent voltage ( input/output ) - filter connection for the internal quiescent reference voltage. va 19 analog power ( input ) - positive power supply for the analog section. ref_gnd 23 reference ground ( input ) - ground reference for the internal sampling circuits. filt+ 24 positive voltage reference ( output ) - positive reference voltage for the internal sampling circuits.
cs5351 ds565pp2 5 2 typical connection diagram filt+ v d 0.1 f a/d converter sclk cs5351 m/s mclk ainl ainr vq 47 f + rst va v l +5v 1 f +5v to 2.5v 5.1 ? 1 f + + + sdout gnd i 2 s/lj lrck gnd power down and mode settings audio data processor timing logic and clock 0.1 f 0.1 f 0.1 f 0.1 f hpf m0 m1 refgnd mdiv +5 v to 3.3 v 1 f 0.1 f 1 f + analog input buffer (figure 3) ovfl vl 10 k ? 3 vq 2 vq 1 figure 1. typical connection diagram
cs5351 6 ds565pp2 3 applications 3.1 operational mode/sample rate range select the output sample rate, fs, can be adjusted from 2khz to 192khz. the cs5351 must be set to the proper speed mode via the mode pins, m1 and m0. refer to table 1. 3.2 system clocking the device supports operation in either master mode, where the left/right and serial clocks are synchro- nously generated on-chip, or slave mode, which requires external generation of the left/right and serial clocks. the device also includes a master clock divider in master mode where the master clock will be internally divided prior to any other internal circuitry when mdiv is enabled, set to logic 1. in slave mode the mdiv pin needs to be disabled, set to logic 0. m1 (pin 14) m0 (pin 13) mode output sample rate (fs) 0 0 single speed mode 2khz - 50khz 0 1 double speed mode 50khz - 100khz 1 0 quad speed mode 100khz - 192khz 11reserved table 1. cs5351 mode control
cs5351 ds565pp2 7 3.2.1 master mode in master mode, lrck and sclk operate as outputs. the left/right and serial clocks are internally derived from the master clock with the left/right clock equal to fs and the serial clock equal to 64x fs, as shown in figure 2. refer to table 2 for common master clock frequencies 128 256 64 m0 m1 lrck output (equal to fs) single speed quad speed double speed 00 01 10 2 4 1 sclk output single speed quad speed double speed 00 01 10 2 1 0 1 mclk mdiv figure 2. cs5351 master mode clocking sample rate (khz) mdiv = 0 mclk (mhz) mdiv = 1 mclk (mhz) 32 8.192 16.384 44.1 11.2896 22.5792 48 12.288 24.576 64 8.192 16.384 88.2 11.2896 22.5792 96 12.288 24.576 176.4 11.2896 22.5792 192 12.288 24.576 table 2. cs5351 common master clock frequencies
cs5351 8 ds565pp2 3.2.2 slave mode lrck and sclk operate as inputs in slave mode. the left/right clock must be synchronously derived from the master clock and be equal to fs. it is also recommended that the serial clock be synchronously derived from the master clock and be equal to 64x fs to maximize system performance. refer to table 3 for required clock ratios. *available when mdiv = 1 (for master mode) table 3. cs5351 slave mode clock ratios 3.3 power-up sequence reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and configuration pins are stable. it is also recommended that reset be enabled if the analog or digital supplies drop below the minimum specified operating voltages to prevent power glitch related issues. the internal reference voltage must be stable for the device to produce valid data. therefore, there is a de- lay between the release of reset and the generation of valid output, due to the finite output impedance of filt+ and the presence of the external capacitance. 3.4 analog connections the analog modulator samples the input at 6.144 mhz (mclk=12.288 mhz). the digital filter will reject signals within the stopband of the filter. however, there is no rejection for input signals which are (n 6.144 mhz) the digital passband frequency, where n=0,1,2,...refer to figure 3 which shows the sug- gested filter that will attenuate any noise energy at 6.144 mhz, in addition to providing the optimum source impedance for the modulators. the use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity. please see the addendum at the end of the datasheet for an analog input buffer that can be used with both the cs5351 as well as the cs5361 with a simple change in the bill of materials. single speed mode fs = 2khz to 50khz double speed mode fs = 50khz to 100khz quad speed mode fs = 100khz to 192khz mclk/lrck ratio 256x (512x)* 128x (256x)* 128x (256x)* sclk/lrck ratio 32x, 64x, 128x 32x, 64x 64x
cs5351 ds565pp2 9 3.5 high pass filter and dc offset calibration the operational amplifiers in the input circuitry driving the cs5351 may generate a small dc offset into the a/d converter. the cs5351 includes a high pass filter after the decimator to remove any dc offset which could result in recording a dc level, possibly yielding "clicks" when switching between devices in a multichannel system. the high pass filter continuously subtracts a measure of the dc offset from the output of the decimation filter. if the hpf pin is taken high during normal operation, the current value of the dc offset register is frozen and this dc offset will continue to be subtracted from the conversion result. this feature makes it possible to perform a system dc offset calibration by: 1) running the cs5351 with the high pass filter enabled until the filter settles.see the digital filter char- acteristics for filter settling time. 2) disabling the high pass filter and freezing the stored dc offset. a system calibration performed in this way will eliminate offsets anywhere in the signal path between the calibration point and the cs5351. 3.6 overflow detection the cs5361 includes overflow detection on both the left and right channels. this time multiplexed infor- mation is presented as open drain, active low on pin 15, ovfl . the ovfl_l and ovfl_r data will go to a logical low as soon as an overrange condition in either channel is detected. the data will remain low vq 10k ? + 634 ? 634 ? 91 ? 91 ? + - - 2700 pf 470 pf 470 pf cog cog 100 uf 100 uf cs5351 ainl cs5351 ainr ain l ain r cog 10k ? 2700 pf cog figure 3. cs5351 recommended analog input buffer
cs5351 10 ds565pp2 as specified in the switching characteristics - serial audio port section. this ensures sufficient time to detect an overrange condition regardless of the speed mode. after the timeout, the ovfl_l and ovfl_r data will return to a logical high if there has not been any other overrange condition detected. please note that an overrange condition on either channel will restart the timeout period for both channels. 3.6.1 ovfl output timing in left-justified format, the ovfl pin is updated one sclk period after an lrck transition. in i 2 s format, the ovfl pin is updated two sclk periods after an lrck transition. refer to figures 23 and 24. in both cases the ovfl data can be easily demultiplexed by using the lrck to latch the data. in left-justified format, the rising edge of lrck would latch the right channel overflow status, and the falling edge of lrck would latch the left channel overflow status. in i 2 s format, the falling edge of lrck would latch the right channel overflow status and the rising edge of lrck would latch the left channel overflow status. 3.7 grounding and power supply decoupling as with any high resolution converter, the cs5351 requires careful attention to power supply and ground- ing arrangements if its potential performance is to be realized. figure 1 shows the recommended power arrangements, with va and vl connected to clean supplies. vd, which powers the digital filter, may be run from the system logic supply or may be powered from the analog supply via a resistor. in this case, no additional devices should be powered from vd. decoupling capacitors should be as near to the adc as possible, with the low value ceramic capacitor being the nearest. all signals, especially clocks, should be kept away from the filt+ and vq pins in order to avoid unwanted coupling into the modulators. the filt+ and vq decoupling capacitors, particularly the 0.1 f, must be positioned to minimize the electri- cal path from filt+ and refgnd. the cdb5351 evaluation board demonstrates the optimum layout and power supply arrangements. to minimize digital noise, connect the adc digital outputs only to cmos inputs. 3.8 synchronization of multiple devices in systems where multiple adcs are required, care must be taken to achieve simultaneous sampling. to ensure synchronous sampling, the mclk and lrck must be the same for all of the cs5351?s in the sys- tem. if only one master clock source is needed, one solution is to place one cs5351 in master mode, and slave all of the other cs5351?s to the one master. if multiple master clock sources are needed, a possible solution would be to supply all clocks from the same external source and time the cs5351 reset with the inactive edge of mclk. this will ensure that all converters begin sampling on the same clock edge.
cs5351 ds565pp2 11 4 characteristics and specifications analog characteristics (CS5351-KS/kz) (test conditions (unless otherwise speci- fied): input test signal is a 1 khz sine wave; measurement bandwidth is 10 hz to 20 khz. typical performance char- acteristics are derived from measurements taken at t a =25 c, vl = vd = 3.3v and va = 5.0v. min/max performance characteristics are guaranteed over the specified operating temperature and voltages.) note: 1. referred to the typical full-scale input voltage parameter symbol min typ max unit single speed mode fs = 48khz dynamic range a-weighted unweighted 102 99 108 105 - - db db total harmonic distortion + noise (note 1) -1 db -20 db -60 db thd+n - - - -98 -85 -45 -92 - - db db db double speed mode fs = 96khz dynamic range a-weighted unweighted 40khz bandwidth unweighted 102 99 - 108 105 102 - - - db db db total harmonic distortion + noise (note 1) -1 db -20 db -60 db 40khz bandwidth -1db thd+n - - - - -98 -85 -45 -95 -92 - - - db db db db quad speed mode fs = 192khz dynamic range a-weighted unweighted 40khz bandwidth unweighted 102 99 - 108 105 102 - - - db db db total harmonic distortion + noise (note 1) -1 db -20 db -60 db 40khz bandwidth -1db thd+n - - - - -98 -85 -45 -95 -92 - - - db db db db dynamic performance for all modes interchannel isolation - 95 - db interchannel phase deviation - 0.0001 - degree dc accuracy interchannel gain mismatch - 0.1 - db gain error - 5 % gain drift - 100 - ppm/ c offset error hpf enabled hpf disabled - - 0 100 - - lsb lsb analog input characteristics full-scale input voltage 0.95 1.0 1.05 vrms input impedance 18 - - k ?
cs5351 12 ds565pp2 analog characteristics (cs5351-bs/bz) (test conditions (unless otherwise speci- fied): input test signal is a 1 khz sine wave; measurement bandwidth is 10 hz to 20 khz. typical performance char- acteristics are derived from measurements taken at t a =25 c, vl = vd = 3.3v and va = 5.0v. min/max performance characteristics are guaranteed over the specified operating temperature and voltages.) parameter symbol min typ max unit single speed mode fs = 48khz dynamic range a-weighted unweighted 101 98 108 105 - - db db total harmonic distortion + noise (note 1) -1 db -20 db -60 db thd+n - - - -98 -85 -45 -91 - - db db db double speed mode fs = 96khz dynamic range a-weighted unweighted 40khz bandwidth unweighted 101 98 - 108 105 102 - - - db db db total harmonic distortion + noise (note 1) -1 db -20 db -60 db 40khz bandwidth -1db thd+n - - - - -98 -85 -45 -95 -91 - - - db db db db quad speed mode fs = 192khz dynamic range a-weighted unweighted 40khz bandwidth unweighted 101 98 - 108 105 102 - - - db db db total harmonic distortion + noise (note 1) -1 db -20 db -60 db 40khz bandwidth -1db thd+n - - - - -98 -85 -45 -95 -91 - - - db db db db dynamic performance for all modes interchannel isolation - 95 - db interchannel phase deviation - 0.0001 - degree dc accuracy interchannel gain mismatch - 0.1 - db gain error - 5% gain drift - 100 - ppm/ c offset error hpf enabled hpf disabled - - 0 100 - - lsb lsb analog input characteristics full-scale input voltage 0.9 1.0 1.1 vrms input impedance 18 - - k ?
cs5351 ds565pp2 13 digital decimation filter characteristics notes: 2. response shown is for fs equal to 48 khz. filter characteristics scale with fs. 3. the filter frequency response scales precisely with fs. parameter symbol min typ max unit single speed mode (2khz to 50khz sample rates) passband (-0.1 db) (note 3) 0 - 0.47 fs passband ripple - - 0.035 db stopband (note 3) 0.58 - - fs stopband attenuation -95 - - db total group delay (fs = output sample rate) t gd -12/fs- s group delay variation vs. frequency ? t gd --0.0 s double speed mode (50khz to 100khz sample rates) passband (-0.1 db) (note 3) 0 - 0.45 fs passband ripple - - 0.035 db stopband (note 3) 0.68 - - fs stopband attenuation -92 - - db total group delay (fs = output sample rate) t gd -9/fs- s group delay variation vs. frequency ? t gd --0.0 s quad speed mode (100khz to 192khz sample rates) passband (-0.1 db) (note 3) 0 - 0.24 fs passband ripple - - 0.035 db stopband (note 3) 0.78 - - fs stopband attenuation -97 - - db total group delay (fs = output sample rate) t gd -5/fs- s group delay variation vs. frequency ? t gd --0.0 s high pass filter characteristics frequency response -3.0 db -0.13 db (note 2) -1 20 - - hz hz phase deviation @ 20hz (note 2) - 10 - deg passband ripple - - 0 db filter settling time 10 5 /fs s
cs5351 14 ds565pp2 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 frequency (normalized to fs) amplitude (db) figure 4. single speed mode stopband rejection figure 5. single speed mode transition band -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.05 -0.03 0.00 0.03 0.05 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (normalized to fs) amplitude (db) figure 6. single speed mode transition band (detail) figure 7. single speed mode passband ripple -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.00.10.20.30.40.50.60.70.80.91.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.43 0.45 0.48 0.50 0.53 0.55 0.58 0.60 0.63 0.65 0.68 0.70 frequency (normalized to fs) amplitude (db) figure 8. double speed mode stopband rejection figure 9. double speed mode transition band
cs5351 ds565pp2 15 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.40 0.43 0.45 0.48 0.50 0.53 0.55 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.05 -0.03 0.00 0.03 0.05 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (normalized to fs) amplitude (db) figure 10. double speed mode transition band (detail) figure 11. double speed mode passband ripple -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 frequency (normalized to fs) amplitude (db) -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 frequency (normalized to fs) amplitude (db) figure 12. quad speed mode stopband rejection figure 13. quad speed mode transition band -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 frequency (normalized to fs) amplitude (db) figure 14. quad speed mode transition band (detail) figure 15. quad speed mode passband ripple
cs5351 16 ds565pp2 dc electrical characteristics (gnd = 0v, all voltages with respect to ground. mclk=12.288 mhz; master mode) notes: 4. power down mode is defined as rst = low with all clocks and data lines held static. 5. valid with the recommended capacitor values on filt+ and vq as shown in the typical connection diagram. digital characteristics thermal characteristics parameter symbol min typ max unit dc power supplies: positive analog positive digital positive logic va vd vl 4.75 3.1 2.37 5.0 - - 5.25 5.25 5.25 v v v power supply current va (normal operation) vl,vd = 5 v vl,vd = 3.3v i a i d i d - - - 17.5 22 14.5 21 26 17 ma ma ma power supply current va (power-down mode)(note 4) vl,vd=5v i a i d - - 2 2 - - ma ma power consumption (normal operation) vl, vd=5v vl, vd = 3.3v (power-down mode) - - - - - - 198 135 20 235 161 - mw mw mw power supply rejection ratio (1 khz) (note 5) psrr - 65 - db v q nominal voltage output impedance maximum allowable dc current source/sink - - - 2.5 25 0.01 - - - v k ? ma filt+ nominal voltage output impedance maximum allowable dc current source/sink - - - 5 35 0.01 - - - v k ? ma parameter symbol min typ max units high-level input voltage (% of vl) v ih 70% - - v low-level input voltage (% of vl) v il --30%v high-level output voltage at i o = 100 ua (% of vl) v oh 70% - - v low-level output voltage at i o =100 ua (% of vl) v ol --15%v ovfl current sink i ovfl --4.0ma input leakage current i in -- 10 a parameter symbol min typ max unit allowable junction temperature - - 135 c junction to ambient thermal impedance ja -70 - c/w ambient operating temperature (power applied) -ks/kz -bs/bz t a t a -10 -40 - - +70 +85 c c
cs5351 ds565pp2 17 absolute maximum ratings (gnd = 0v, all voltages with respect to ground.) (note 8) notes: 6. any pin except supplies. transient currents of up to 100 ma on the analog input pins will not cause src latch-up. 7. the maximum over/under voltage is limited by the input current. 8. operation beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. parameter symbol min typ max units dc power supplies: analog logic digital va vl vd -0.3 -0.3 -0.3 - - - +6.0 +6.0 +6.0 v v v input current (note 6) i in -- 10 ma analog input voltage (note 7) v in gnd-0.7 - va+0.7 v digital input voltage (note 7) v ind -0.7 - vl+0.7 v ambient operating temperature (power applied) t a -50 - +95 c storage temperature t stg -65 - +150 c
cs5351 18 ds565pp2 switching characteristics - serial audio port (logic "0" = gnd = 0 v; logic "1" = vl = 2.37v to 5.25v, va = 5v 5%, vd = 3.1v to 5.25v, c l =20pf) parameter symbol min typ max unit input sample rate single speed mode double speed mode quad speed mode fs fs fs 2 50 100 - - - 50 100 192 khz khz khz ovfl to lrck edge setup time t setup 16/f sclk --s ovfl to lrck edge hold time t hold 1/f sclk --s ovfl time-out on overrange condition fs = 44.1, 88.2, 176.4khz fs = 48, 96, 192khz - - 740 680 - - ms ms mclk specifications mclk period t clkw 40 - 1953 ns mclk pulse width high t clkh 15 - - ns mclk pulse width low t clkl 15 - - ns master mode sclk falling to lrck t mslr -20 - 20 ns sclk falling to sdout valid t sdo 0 - 40 ns sclk duty cycle - 50 - % sclk output frequency - 50 - % slave mode single speed output sample rate fs 2 - 50 khz lrckdutycycle 405060% sclk period t sclkw 163 - - ns sclk high/low t sclkhl 20 - - ns sclk falling to sdout valid t dss - - 40 ns sclk falling to lrck edge t slrd -20 - 20 ns double speed output sample rate fs 50 - 100 khz lrckdutycycle 405060% sclk period t sclkw 163 - - ns sclk high/low t sclkhl 20 - - ns sclk falling to sdout valid t dss - - 40 ns sclk falling to lrck edge t slrd -20 - 20 ns quad speed output sample rate fs 100 - 192 khz lrckdutycycle 405060% sclk period t sclkw 81 - - ns sclk high/low t sclkhl 20 - - ns sclk falling to sdout valid t dss - - 20 ns sclk falling to lrck edge t slrd -10 - 10 ns
cs5351 ds565pp2 19 sclk output t msl r sdout t sd o lrck output msb msb-1 sclk input lrck input sclkl t dss t msb msb-1 msb-2 lrdss t sclkh t t sclkw sdout srd l t figure 16. master mode, left justified sai figure 17. slave mode, left justified sai sclk output t mslr sdout t sdo lrck output msb sclk input lrck input sclkl t dss t msb msb-1 sclkh t t sclkw sdout figure 18. master mode, i 2 s sai figure 19. slave mode, i 2 ssai ovfl t setup lrck t hold figure 20. ovfl output timing
cs5351 20 ds565pp2 sdata 23 22 7 6 23 22 sclk lrck 23 22 54 32 10 8 76 54 32 10 8 9 9 left channel right channel figure 21. left-justified serial audio interface sdata 23 22 8 7 23 22 sclk lrck 23 22 65 43 21 0 87 65 43 21 0 9 9 left channel right channel figure 22. i 2 s serial audio interface lrck ovfl sclk ovfl_r ovfl_l ovfl_r figure 23. ovfl output timing, i 2 sformat lrck ovfl sclk ovfl_r ovfl_l ovfl_r figure 24. ovfl output timing, left-justified format
cs5351 ds565pp2 21 5 parameter definitions dynamic range the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is added to resulting measurement to refer the measurement to full-scale. this technique ensures that the distortion components are below the noise level and do not affect the measurement. this measurement technique has been accepted by the audio engineering society, aes17-1991, and the electronic industries association of japan, eiaj cp-307. expressed in decibels. total harmonic distortion + noise the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 hz to 20 khz), including distortion components. expressed in decibels. measured at -1 and -20 dbfs as suggested in aes17-1991 annex a. frequency response a measure of the amplitude response variation from 10 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel isolation a measure of crosstalk between the left and right channels. measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full-scale analog output for a full-scale digital input. gain drift the change in gain value with temperature. units in ppm/ c. offset error the deviation of the mid-scale transition (111...111 to 000...000) from the ideal. units in mv.
cs5351 22 ds565pp2 6 package dimensions inches millimeters dim min max min max a 0.093 0.104 2.35 2.65 a1 0.004 0.012 0.10 0.30 b 0.013 0.020 0.33 0.51 c 0.009 0.013 0.23 0.32 d 0.598 0.614 15.20 15.60 e 0.291 0.299 7.40 7.60 e 0.040 0.060 1.02 1.52 h 0.394 0.419 10.00 10.65 l 0.016 0.050 0.40 1.27 0 8 0 8 24l soic (300 mil body) package drawing d h e b a1 a c l seating plane 1 e
cs5351 ds565pp2 23 notes: 1. ? d ? and ? e1 ? are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension ? b ? does not include dambar protrusion/intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of ? b ? dimension at maximum material condition. dambar intrusion shall not reduce dimension ? b ? by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a -- -- 0.043 -- -- 1.10 a1 0.002 0.004 0.006 0.05 -- 0.15 a2 0.03346 0.0354 0.037 0.85 0.90 0.95 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 d 0.303 0.307 0.311 7.70 7.80 7.90 1 e 0.248 0.2519 0.256 6.30 6.40 6.50 e1 0.169 0.1732 0.177 4.30 4.40 4.50 1 e -- 0.026 bsc -- -- 0.65 bsc -- l 0.020 0.024 0.028 0.50 0.60 0.70 0 4 8 0 4 8 jedec #: mo-153 controlling dimension is millimeters. 24l tssop (4.4 mm body) package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
cs5351 24 ds565pp2 7 addendum the cs5351 and cs5361 family of analog-to-digi- tal converters are functionally compatible and can easily be interchanged with minimal modifications to the input buffer circuitry. figure 25 shows an analog input buffer that pro- vides anti-alias filtering, proper dc biasing, and op- timum source impedance for the modulators. the input buffer shown will work well with both the cs5351 and the cs5361, merely by changing the bill of materials. in order to use this buffer design with the cs5351, one would stuff the 0ohm resistors r19 and r22 and not populate r3 and r20. this will create a sin- gle-ended input buffer (as shown in figure 3) with the unused differential input pin connected to the quiescent voltage of the converter (vq). note that in this configuration, it is unnecessary to have the second op-amp and related components. in order to use this buffer design with the cs5361, one would stuff the 0ohm resistors r3 and r20 and not populate r19 and r22. this will create a fully differential analog input buffer. figure 25. cs5351/cs5361 analog input buffer

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